| Title |
High Speed Accelerators Hardware Implementation for Fully Connected Neural Network Model Using 3D Systolic Array Architecture |
| Authors |
(Pottipati Dileep Kumar Reddy) ; (Kota Venakata Ramanaih) |
| DOI |
https://doi.org/10.5573/IEIESPC.2026.15.3.452 |
| Keywords |
CNN; FCNN; MPL; Systolic array |
| Abstract |
In Convolution Neural Network (CNN) is a primary building block for image processing applications with sub systems such as Convolution layer (CL), Max pooling Layer (MPL) & Fully Connected Neural Network (FCNN) layer. In order to address computation complexity of FCNN model in terms of processing speed, hardware implementation on FPGA is required to assess and optimize. In this study, systolic array algorithm-based 3D structure is developed to implement FCNN model. The 3D structure processes multiple frames of input data with three filters to generate simultaneously the FCNN output using multistage FCNN model. The processing elements that form the primary building block of systolic array model is designed suing basic arithmetic elements and control circuit for data synchronization. Verilog HDL is developed for the proposed model along with test bench to verify the functionality and the 3D structure with pipelined logic is implemented on Virtex-5 FPGA and form the synthesis report it is estimated that the operating frequency is 277 MHz which is 27% faster than direct implementation, power dissipation is also increased by 6% with tradeoff with computation speed. The 3D CNN structure is suitable for high-speed image processing applications. |