| Title |
An Evaluation of Burst Transfer Inferred by a High-level Synthesis Tool |
| Authors |
Yuki Yamagata(Yuki Yamagata) ; Akira Yamawaki(Akira Yamawaki) |
| DOI |
https://doi.org/10.5573/IEIESPC.2019.8.2.143 |
| Keywords |
Burst transfer ; High-level synthesis ; Memory access ; Reconfigurable device ; High performance |
| Abstract |
High-level synthesis (HLS) is technology that automatically converts software to digital hardware. HLS has gained attention as a promising technology that can reduce the burden of hardware development. However, if a software program converted by HLS does not consider organization of the hardware, the current HLS technology cannot convert software to proper digital hardware. One of the characteristics of the hardware to be considered is burst transfer to memory access. Burst transfer attempts to speed up memory access by packing continuous data into a single address. This paper discusses a rectangle-drawing case study that demonstrates how to describe a C program so an HLS tool can infer burst transfer with an arbitrary burst length. Moreover, we consider the necessity to suppress optimization performed by the HLS tool to prevent increasing the amount of digital hardware when we implement the arbitrary burst length. Experiments clarify how performance and the hardware scale change based on the difference in the burst length and suppression of optimization. |