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Title A Fast (7, 3)-adder Circuit for High-speed Multiplier Design
Authors (Myungchul Yoon)
Page pp.298-303
ISSN 2287-5255
Keywords Adder; (m; 3)-adder; Multiplier; Multiplier design; Adder circuit
Abstract A set of fast (m, 3)-adder circuits (4 ≤ m ≤ 7) is presented in this paper. An (m, 3)-adder adds m bits at a time and produces three outputs (N, C, S). These adders are designed to implement high-speed (7, 3)-adder based multipliers that use a (7, 3)-adder as a basic unit and five other adders ((6, 3), (5, 3), (4, 3), (3, 2), and (2, 2)-adder) as auxiliary units for the addition of partial products.
Multipliers require adding tens of partial products to obtain a result, and they can be added by (7, 3)-adders more quickly than by (3, 2)-adders. In simulation results, the worst-case delay and power of the new (7, 3)-adder are 1.45 times and 2.4 times larger than those of the reference (3, 2)-adder.
However, the parallel addition of partial products with the (7, 3)-adder is faster and consumes less power than with the (3, 2)-adder because the (7, 3)-adder based multiplier requires fewer adders and addition stages than a (3, 2)-adder based multiplier. This result shows that the speed of a multiplier can be increased by using (7, 3)-adders instead of (3, 2)-adders in reducing partial products.