| Title |
Digital Post-processing Techniques for Time-interleaved ADCs |
| Authors |
(Hongmei Chen) ; (Lanyu Wang) ; (Jian Wang) ; (Jiashen Li) ; (Honghui Deng) ; (Xu Meng) ; (Yongsheng Yin) |
| DOI |
https://doi.org/10.5573/IEIESPC.2022.11.6.462 |
| Keywords |
Digital post-processing circuit; Time-interleaved ADC; All-digital calibration; Down conversion |
| Abstract |
This paper presents an all-digital post-processing circuit for a high-speed and highprecision time-interleaved ADC (TIADC). By pre-inputting a test signal in the TIADC, channel mismatch errors are estimated and stored, and the stored values are extracted to compensate for errors when the input signal is at a special frequency. The frequency can be detected by a threshold judgement module. This solves the problem of the traditional modulation calibration algorithm, which cannot calibrate the signal at a special frequency. A high-speed low-complexity digital down converter (DDC) circuit with an optional decimation ratio of 1, 2, 4, or 8 times was designed to have different frequency outputs of the TIADC. We applied it to a four-channel 14-bit 360-MHz TIADC system with an input signal fin of 110 MHz. The FPGA verification results show that after calibration and decimation, the spurious-free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) improve by about 40 dB and 30 dB, respectively. |