| Title |
Optimized Distributive Arithmetic-based Hardware Accelerator for Dual Tree Complex Wavelet Transform Computation |
| Authors |
(Computation Yashavanthakumar T. R.) ; (Sampathrao L. Pinjare) ; (Cyril Prasanna Raj P.) |
| DOI |
https://doi.org/10.5573/IEIESPC.2023.12.1.38 |
| Keywords |
Distributive arithmetic algorithm; Memory efficient; Wavelet transform; Image processing; FPGA |
| Abstract |
Hardware architectures for fast computation of complex wavelet transforms for image processing require optimized design approaches. The Dual Tree Complex Wavelet Transform (DTCWT) is twice as complex as the Discrete Wavelet Transform (DWT) and was designed while considering the distributive arithmetic (DA) algorithm, which is customized for the design of a 10- tap filter architecture. Redundancy in the filter coefficients was considered in optimizing the DA partial products, reducing the area resources by 97.65%. The reduced architecture was modeled in Verilog HDL and implemented on a Xilinx FPGA. The operating frequency is 312 MHz, and the power dissipation is less than 1 W. The proposed model is suitable for high-speed computation of DTCWT sub-bands on an FPGA platform. |