1. Introduction

Recently, technologies such as the Internet of Things, autonomous driving, virtual reality, and artificial intelligence have been rapidly developing. It is expected that these technologies will provide various application services based on big data in the near future. In order for the application technology of big data to be implemented, high-performance computing using semiconductors is required. Dynamic Random Access Memory (DRAM) is widely used as main memory in various technical fields. Recently, the technology trend in DRAM products has been progressing toward high-speed operation and high capacities. In addition, it is necessary to reliably inspect signal quality for high-performance DRAM products, and the importance of test parts and equipment is gradually increasing.

The memory socket board corresponds to an interface that transmits high-speed signals generated from the main body of the test equipment to a memory device such as DRAM. The memory socket board must stably transmit various signals operating at high speed without distortion. Therefore, in memory socket board design, it is necessary to reduce signal reflection and crosstalk through impedance matching [1-4], and reduce resonance and power noise through the setup of decoupling capacitors and their placement [5-7]. In this analysis, electromagnetic field simulation and data channel simulation are performed. Based on these simulation results, signal integrity and power integrity analysis of the memory socket board are carried out [1]. Through these analysis results, signal quality can be predicted at the board design stage, and stable signal characteristics can be obtained by changing the board design.

Various studies on signal integrity and power integrity at the board level have been conducted. In order to realize low power distribution network (PDN) impedance and high data-rate operation, a method of applying the power layer arrangement and a stubless signal via the technology in a board stack structure was proposed [8]. The result of signal integrity analysis has been reported to improve the crosstalk margin between adjacent signals, reducing the insertion loss of a signal trace by adopting a hybrid stacked structure on the board [9]. In addition, the effect of PDN impedance on the selection of different types of decoupling capacitors and their location was analyzed in the design of the interposer [10].

The operation speed of semiconductor products has been gradually increasing, and test technologies have also been developed to enable high-speed operation accordingly, while a low-cost test process must be maintained at the same time [11]. One of the main challenges of the test fixture interface is to achieve high performance while implementing a high-density memory socket board design to achieve low cost. In this paper, we reduce the layer stackup of the board, design memory socket boards by applying a split layout to the power plane and a low-cost dielectric, and we analyze the changes in their electrical performance. The scope of the board stack design in this paper includes layer stackup change, power plane layout, and dielectric change.

2. Design of Memory Socket Board

The test fixture interface inside the memory test system is largely composed of a motherboard and a socket board. The two boards are connected to each other by coaxial cables and connectors, and the socket board is connected to the device under test (DUT) through a test socket.

Fig. 1 shows the structure of the test fixture interface. The memory socket board receives the signal transmitted from the connector and transmits it to the test socket pad while maintaining high-speed operation and a high-quality signal. Therefore, in order to achieve these characteristics, the design of the memory socket board should be done with a signal wiring interval of 3-W or more. This design method can provide a significant performance margin in terms of signal integrity, but it decreases the efficiency of the signal wiring area, and then causes an increase in the layer stackup of the board, which in turn increases the test cost. In a previous study applying a board design based on the 3-W wiring spacing rule, it was possible to reduce the total of eight layers, including four signal layers and four VSS layers [12]. In this paper, based on the 3-W wiring spacing rule, the VDDQ layer and the VPP layer are reduced to a single layer (the VDDQ-VPP layer), divided power planes are designed onto the VDDQ-VPP layer, and an FR4 epoxy-based low-cost dielectric is applied to the memory socket board. The electrical performance of the boards due to the board stack design changes was analyzed.

Fig. 2 shows the outline of the memory socket board and the wiring schematic of one layer inside the board using the 3-W wiring spacing rule. A number of test socket pads and wiring lines are arranged on the top layer, while connector pads and traces connected to them are routed on the bottom layer. The DUT of this study is a DDR4 78 Ball FBGA connected to the memory socket board through a test socket. Fig. 3 shows the layer stackup types for the memory socket board applied in this study. Stackup A has a VDDQ layer and a VPP layer, whereas Stackup B has the integrated VDDQ-VPP layer as a single layer, with the power layer and ground layer reduced to one layer instead of two. Through-hole vias are applied for interlayer connections of signal and power wiring. Fig. 4 shows each type of power plane design. In Stackup A, VDDQ and VPP power planes are arranged on the entire board in each separate layer, whereas in Stackup B, divided power planes are arranged on the one VDDQ-VPP layer. Table 1 summarizes the material properties of the dielectric used in the board. Dielectric A is used for high-speed operation, and exhibits relatively low dielectric loss. The dielectric constant and dielectric loss of Dielectric B are within the general range widely used in boards and are suitable for low cost.

Fig. 1. The test fixture interface and the memory socket board for a memory device.

Fig. 2. Outline of the memory socket board, and the wiring schematic of one layer inside the board.

Fig. 3. Layer stackup of the memory socket board.

Fig. 4. Layout of VDDQ and VPP planes on the two boards with different stackup layers.

3. Electrical Performance Analysis of the Memory Socket Board

3.1 Analysis of the Layer Stackup Change

The two board designs were implemented by applying the layer stackup shown in Fig. 3, and the split layout of the power plane was designed on the board for Stackup B. Dielectric A in Table 1 was used as the insulating material for the two boards. S-parameter, PDN impedance, and eye-diagram simulations were performed to analyze the effect of the electrical performance of the memory socket board. The simulation frequency range was designated up to 8~GHz in consideration of the maximum operating frequency of the DDR4 memory device and the 5th harmonic range. The selected line for simulation was DQ5; the connector pad and the socket pad on the board were set as ports, and the reference plane was set to VSS. Fig. 5 shows the insertion loss of the DQ5 line from changing the layer stackup. The insertion loss graphs of the DQ5 line show almost the same characteristics over the entire frequency range. This result indicates that no additional loss or attenuation of the signal line occurs, even if the layer stackup is changed. Therefore, although the VDDQ and VPP power plane design was changed by changing the layer stackup, it was confirmed that the difference in insertion loss of the signal line was not significant.

The number of board layers was reduced by changing the layer stackup, which may affect the PDN impedance. Accordingly, the PDN impedance was calculated for each layer stackup type, and Fig. 6 shows the VDDQ-VSS impedance of the boards. The impedances of the two types show almost the same trend up to approximately 0.6 GHz. However, in the frequency band from 0.6 to 1.6 GHz, Stackup B has higher impedance, compared to Stackup A. Stackup B was designed with separate VDDQ and VPP power planes on a single layer, reducing the area of both power planes, compared to Stackup A, which leads to reduced capacitance and increased inductance. This gives Stackup B high impedance in this frequency band.

Eye-diagram simulation was performed to analyze the effect of the frequency domain on the time domain. Fig.~7 shows the DQ5 channel configuration for the eye-diagram simulation. The voltage regulator module (VRM) provides DC 1.2 V, and is connected to the power side of the board. The S-parameters of the signal line and PDN were calculated using ANSYS SIwave. The configuration of the transmitting and receiving terminal was modeled with the input/output buffer information specification (IBIS) and pseudo-random binary sequence (PRBS) operating at 3.2 Gbps. The rise time and unit interval of the buffer were set to 0.09 ns and 0.3125 ns, respectively. Eye-diagram simulations were performed using ANSYS Designer. Fig. 8 shows the calculation result of the DQ5 channel for the layer stackup change. It confirmed that the layer stackup type does not cause a significant difference in the eye-diagram results in terms of timing aperture and voltage margin. Unlike the difference in the PDN impedance, as seen in Fig. 6, these results demonstrate that the power plane split layout design does not affect implementation of 3.2 Gbps operation of the memory socket board.

Fig. 5. Insertion loss of DQ5 trace on the boards with two types of layer stackup.

Fig. 6. VDDQ-VSS impedance on the boards with two types of layer stackup.

Fig. 7. Circuit schematic for eye-diagram simulation.

Fig. 8. Eye-diagram of DQ5 channel on the boards with different layer stackups.

3.2 Analysis of the Dielectric Change

The changes in electrical performance due to the dielectric change of the memory socket board were analyzed through simulations of the S-parameter, PDN impedance, and eye-diagram. When designing the Stackup A and Stackup B boards with Dielectric A in Section 3.1, the width of the signal line was set to 0.09 mm in order to obtain the characteristic impedance of 50 ${\Omega}$. When the dielectric of the board was changed to Dielectric B, the width of the line had to be reduced to obtain the characteristic impedance of 50 ${\Omega}$, which leads to an increase in board manufacturing costs. In this section, two types of dielectrics were applied to a Stackup B board without changing the line width, and the changes in the electrical performance of the board were analyzed.

In order to analyze the effect on the loss of the signal line, the DQ5 line was selected as an analysis vehicle, and its insertion loss was calculated. Fig. 9 shows the insertion loss of the DQ5 line for the dielectric change. Dielectric B shows higher loss characteristics over the entire frequency range. An increase in dielectric constant and capacitance due to the dielectric change reduced the characteristic impedance by 13\% in this work and resulted in impedance mismatch, increasing the insertion loss. Due to the increase in loss tangent, dielectric loss on the line path increased, which also increased the insertion loss. Dielectric changes are known to affect PDN impedance. Fig. 10 shows the VDDQ-VSS impedance of the boards with the two types of dielectric. Dielectric B shows a lower impedance in the frequency bands from 0.5-0.8 GHz, while the two types of dielectrics have almost the same impedance in the frequency bands from 1.2-2.0 GHz. Compared to Dielectric A, the lower impedance of Dielectric B near 0.6 GHz is caused by an increase in capacitance due to an increase in the dielectric constant. However, impedance change hardly ever occurs in the frequency range from 1.0-1.4 GHz since there is no change in inductance. Eye-diagram simulation was performed to analyze the effect of the time domain on the changes in the frequency characteristics in the insertion loss and PDN impedance. The channel configuration and simulation settings are the same as in Fig. 7. Fig. 11 shows the calculation results of the DQ5 channel for the dielectric change. Rising time and falling time increased in Dielectric B, whereas power noise characteristics in Dielectric B improved. Dielectric B had a higher rising time due to a higher loss characteristic in the high-frequency ranges, and had better power noise characteristics due to an overall low VDDQ-VSS impedance. However, if the impedance matching condition for the signal line is satisfied during the design of the memory socket board, it is expected that the insertion loss and the timing aperture characteristics of the board with Dielectric B will improve.

Fig. 9. Insertion loss of DQ5 trace on the board with two types of dielectric.

Fig. 10. VDDQ-VSS impedance on the board with two types of dielectric.

Fig. 11. Eye-diagram of DQ5 channel on the board with two types of dielectric.

4. Conclusion

In this paper, a memory socket board was designed by modifying the layer stackup and the dielectric, and the electrical performance changes were analyzed. By combining the VDDQ layer and the VPP layer in the layer stackup of the board, the power planes were divided while reducing the two layers to one, and a low-cost dielectric based on FR4 epoxy was applied to the board stack design. Analyzing the electrical performance of the board with respect to the changes of the layer stackup, there is little difference in the insertion loss of the DQ5 line, but the PDN impedance increased in some frequency bands. However, the results of the eye-diagram simulation demonstrate that the split layout design of the power planes had no substantial effect on high-speed operation. As a result of analyzing the change in electrical performance due to the dielectric change, the insertion loss of the DQ5 line had a difference in the high-frequency ranges, but the VDDQ-VSS impedance improved. The results of the eye-diagram simulation indicate that the timing characteristics were lower, but the power noise characteristics improved.