3.1 Bootstrapped Switch

In general, the performance of a sample and hold circuit directly and greatly impacts the whole ADC. As the voltage scales down, the sampling circuit becomes a critical part in the SAR ADC because of unwanted effects such as charge injection and clock feedthrough. The bootstrap technique mitigates the problem of signal-dependent on-resistance (R$_{\mathrm{on}}$) of the sampling switch. The on-resistance needs to be kept constant during the sampling phase. When the sampling transistor operates in the deep-triode region, the value of the on-resistance can be expressed as:

Fig. 3 shows the circuit schematic of the bootstrapped switch [3] used in the design. When the sampling clock SCLK is low, both M$_{2}$ and M$_{3}$ turn on and pre-charge the capacitor C$_{\mathrm{B­}}$ to VDD. During the tracking phase, SCLK goes high, and C$_{\mathrm{B}}$ acts as a battery between the gate and source of M$_{\mathrm{s}}$, so the voltage V$_{\mathrm{GS}}$ is approximately 1 V. A minimal length is chosen for M$_{\mathrm{s}}$ to reduce the on-resistance, while a moderate width is chosen to avoid large parasitic and charge injection.

Fig. 3. The circuit schematic of the bootstrapped switch.

3.2 Capacitive DAC

The proposed 10-bit capacitive DAC is illustrated in Fig. 4. Each capacitor is split into two equal fractions (C$_{1}$ to C-$_{9}$), so the common mode voltage V$_{\mathrm{CM}}$ is generated internally. Only one of the split capacitors in each bit cycle needs to switch, which makes the DAC settling faster.

In this structure, the modified version of a V$_{\mathrm{CM}}$-based switching scheme is used for high power efficiency [4]. In the original V$_{\mathrm{CM}}$-based scheme [5], the total number of capacitors is reduced by half in comparison to a conventional switching scheme, which is 512C for a single-ended side. However, this number is still too big and results in a large area on a chip and high power consumption. The number of capacitors in the modified version is reduced much more to only a quarter (256C) of the capacitors necessary in a conventional switching scheme.

In the modified version of the V$_{\mathrm{CM}}$-based switching scheme, the conversion procedure is the same as in the original scheme except for the last significant bit. Fig. 5 shows the switching sequence of this scheme for a 3-bit ADC. In the sampling phase, the input signals V$_{\mathrm{ip}}$ and V$_{\mathrm{in}}$ are stored on the top plate of the capacitor array. V$_{\mathrm{CM}}$ is generated by connecting each divided capacitor part to V$_{\mathrm{ref}}$ and ground. In the conversion phase, the switching process is the same as in the original scheme for the first 9 bits. To determine the LSB, the LSB capacitor of the P-side array just needs to be changed, whereas the N-side array remains unchanged. The waveform of the implemented switching scheme is illustrated in Fig. 6.

When using this scheme, the total switching energy is approximately 85.083CV$_{\mathrm{ref}}$$^{2}$ for 10-bit resolution. This is only 6.24\% of the energy consumption of the conventional scheme and half of energy of the V$_{\mathrm{CM}}$-based scheme. Fig. 7 compares the energy consumption of the three switching schemes.

Fig. 4. The proposed 10-bit capacitive DAC with a modified VCM-based switching scheme.

Fig. 5. Example of 3-bit modified VCM-based switching scheme.

Fig. 6. Waveform of the modified VCM-based switching scheme.

Fig. 7. Switching energy versus output code.

3.3 SAR Control Logic

In this SAR ADC, asynchronous control logic is used to avoid using a high-speed clock generator. As illustrated in Fig. 8, the CLKC generator consists of a comparator, 3-input NAND gate, and delay cell. The comparator acts as an inverter with respect to its input clock CLKC, and the NAND gate is an inverter controlled by the EOC signal. Conceptually, this structure makes up a three-stage ring oscillator [6]. After the falling edge of the sampling clock, oscillation starts, and 10 successive CLKC signals are generated. Each bit cycle is triggered at the rising edge of CLKC. Incomplete settling error may heavily degrade the SAR ADC performance, so a variable delay is designed for the first three largest weighted capacitors to allocate longer time for the DAC to fully settle.

As shown in Fig. 9, a SAR shift register implemented by dynamic logic [7] is used to reduce the power consumption. It consists of 10 bit-slice unit, for which the data is clocked by the READY_B signal. In the conversion phase, whenever a comparison is ready, the bit-slice generates a CYCLE signal to control the DAC switch. Simultaneously, the comparator outputs OUTP and OUTN are loaded, latched, and generate the digital output DOUT[9:0]. Fig. 9(c) shows the DAC control logic for both capacitor arrays.

Fig. 8. Asynchronous clock generator.

Fig. 9. SAR control logic (a) Shift register, (b) Circuit schematic of a bit-slice, (c) DAC control logic.

3.4 Comparator

Fig. 10 shows a diagram of the two-stage dynamic comparator [8]. During the reset phase (CLK=0), transistors M$_{5}$ and M$_{\mathrm{6­}}$ pre-charge nodes Fp and Fn to VDD and cause M$_{12}$ and M$_{14}$ to discharge output nodes Vop and Von to ground. In the regeneration phase (CLK=1), M$_{5}$ and M$_{6}$ turn off, which causes nodes Fp and Fn to discharge from VDD with different rates and yields a voltage difference. The two cross-coupled inverters begin to regenerate when the voltage at nodes Fp and Fn are not high enough for M$_{12}$ and M$_{14}$ to keep discharging outputs to ground. The cascode transistors M$_{3}$ and M$_{4}$ are added to help mitigate the kickback noise that occurs while nodes Fp and Fn discharge.

For every bit comparison to be correct, calibration of the comparator’s offset is inevitable for a SAR ADC. One common way to cancel out the offset in the dynamic comparator is to add one more differential pair parallel to the main input pair. The offset can be eliminated by applying an appropriate DC value to this pair. There are various ways to generate this DC voltage. For low power design, a capacitive DAC that does not consume static power is exploited for offset calibration.

The offset calibration scheme uses a binary weight capacitor array. Fig. 11 shows a diagram of the offset calibration part. As a compromise between area and accuracy, a 5-bit DAC is used for this approach (CAL-DAC). Two bit-slices are added to start the calibration. After all 10 bits are determined, CAL_EN goes high, and the calibration process is begun by shorting the two inputs of the comparator (DACp and DACn) to V$_{\mathrm{CM}}$ to determine the polarity of the offset voltage. If the offset is positive, the capacitor array is connected to CAL-N to compensate for the N-side while CAL-P is shorted to GND, and if the offset is negative, the array is connected to CAL-P.

The circuit was implemented using a 2-to-1 multiplexer. To control the calibration process, simple digital logic was implemented. After the CAL_START signal goes high, a 5-bit counter starts running to generate digital calibration bits CAL[4:0]. The asynchronous clock generator is also used for the calibration. The value of V_CAL on the top plate of the DAC gradually increases until the output of the comparator flips, which means that the offset is calibrated.

At this time, EOC goes high and stops the counter. Immediately, the calibration bit CAL[4:0] is then stored in a register to prepare for the next conversion. In the sampling phase, the top plate of CAL-DAC is shorted to ground for resetting. During normal conversion, the calibration digital code that was previously stored in the register is loaded and applied to CAL-DAC.

Fig. 10. Circuit schematic of two-stage dynamic com-parator.

Fig. 11. Comparator offset calibration (a) Binary-weight capacitor array, (b) Calibration logic, (c) Calibration timing.