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  1. (Department of Electrical and Information Engineering, Seoul National University of Science and Technology / Seoul, Korea {18512108, hkcha} )

SAR ADC, Neural recording system, Asynchronous logic, Biomedical device, Low-power

1. Introduction

In recent years, closed-loop neural system-on-chips (SoCs) with neural recording and stimulation functions have been widely researched for implantable biomedical devices [1]. These systems can improve patients’ quality of life and are capable of diagnosing and treating various neurological conditions, such as Alzheimer’s disease, epilepsy, and Parkinson’s disease. The neural recording path in neural SoCs is a data acquisition and processing system that observes and understands the electrical activity of the neural networks in the brain.

Fig. 1 shows a block diagram of a typical closed-loop neurostimulation system for seizure treatment [2]. The analog-to-digital converter (ADC) in the neural recording path is an important block that acts as an interface between the analog front-end (AFE) and the digital signal-processing control unit. In such systems, low power consumption is very critical as power resources may be limited in an implant environment, and high power consumption may lead to excessive heating in the surroundings, causing tissue damage.

Neural signals include action potentials (APs or spikes) and local field potentials (LFPs), which generally have a bandwidth ranging from 1 Hz to a few kHz. The amplitude ranges from a few hundred ${\mu}$V to several mV. Therefore, the sampling rate of the ADC does not need to be very high to achieve suitable performance. The successive approximation register (SAR) ADC architecture is the best candidate in this context due to its low power and simple architecture, so it was chosen for this work. A 10-bit SAR ADC with a sampling rate of 250 kS/s was chosen after carefully considering the tradeoff between the power consumption and ADC performance.

The rest of the paper is organized as follows. Section 2 presents the architecture of the proposed SAR ADC. Section 3 discusses the design details of the key function blocks in the ADC. Section 4 presents the key simulation results, followed by the conclusions in Section 5.

Fig. 1. Block diagram of a closed-loop neural system-on-chip.

2. Proposed SAR ADC Architecture

Fig. 2 shows the architecture and timing diagram of the proposed 10-bit SAR ADC for a neural recording system. To achieve good common-mode noise rejection, a fully differential structure is used. A bootstrapped sampling circuit is used to improve the linearity when the input signal ranges from 0 to 1 V. In addition, a modified V$_{\mathrm{CM}}$-based switching scheme is used for a binary weighted capacitive digital-to-analog converter (DAC) to reduce the switching energy.

The differential input signal is sampled on the top plates of the capacitor array, so the MSB is determined directly without any switching activity. A dynamic comparator compares the voltage on the top plate of the capacitor array. Asynchronous SAR control logic stores the comparison results as digital output code and generates control signals for the capacitor switching array. All 10 bits are determined successively until the end of conversion (EOC). When the conversion is done, a time interval is allocated for the comparator offset calibration process before a new conversion occurs.

Fig. 2. Architecture of the proposed 10-bit SAR ADC and timing diagram.

3. Key Functional Blocks

3.1 Bootstrapped Switch

In general, the performance of a sample and hold circuit directly and greatly impacts the whole ADC. As the voltage scales down, the sampling circuit becomes a critical part in the SAR ADC because of unwanted effects such as charge injection and clock feedthrough. The bootstrap technique mitigates the problem of signal-dependent on-resistance (R$_{\mathrm{on}}$) of the sampling switch. The on-resistance needs to be kept constant during the sampling phase. When the sampling transistor operates in the deep-triode region, the value of the on-resistance can be expressed as:

$ R_{on}=\frac{1}{\mu _{n}C_{ox}\left(W/L\right)\left(V_{GS}-V_{th}\right)} $

Fig. 3 shows the circuit schematic of the bootstrapped switch [3] used in the design. When the sampling clock SCLK is low, both M$_{2}$ and M$_{3}$ turn on and pre-charge the capacitor C$_{\mathrm{B­}}$ to VDD. During the tracking phase, SCLK goes high, and C$_{\mathrm{B}}$ acts as a battery between the gate and source of M$_{\mathrm{s}}$, so the voltage V$_{\mathrm{GS}}$ is approximately 1 V. A minimal length is chosen for M$_{\mathrm{s}}$ to reduce the on-resistance, while a moderate width is chosen to avoid large parasitic and charge injection.

Fig. 3. The circuit schematic of the bootstrapped switch.

3.2 Capacitive DAC

The proposed 10-bit capacitive DAC is illustrated in Fig. 4. Each capacitor is split into two equal fractions (C$_{1}$ to C-$_{9}$), so the common mode voltage V$_{\mathrm{CM}}$ is generated internally. Only one of the split capacitors in each bit cycle needs to switch, which makes the DAC settling faster.

In this structure, the modified version of a V$_{\mathrm{CM}}$-based switching scheme is used for high power efficiency [4]. In the original V$_{\mathrm{CM}}$-based scheme [5], the total number of capacitors is reduced by half in comparison to a conventional switching scheme, which is 512C for a single-ended side. However, this number is still too big and results in a large area on a chip and high power consumption. The number of capacitors in the modified version is reduced much more to only a quarter (256C) of the capacitors necessary in a conventional switching scheme.

In the modified version of the V$_{\mathrm{CM}}$-based switching scheme, the conversion procedure is the same as in the original scheme except for the last significant bit. Fig. 5 shows the switching sequence of this scheme for a 3-bit ADC. In the sampling phase, the input signals V$_{\mathrm{ip}}$ and V$_{\mathrm{in}}$ are stored on the top plate of the capacitor array. V$_{\mathrm{CM}}$ is generated by connecting each divided capacitor part to V$_{\mathrm{ref}}$ and ground. In the conversion phase, the switching process is the same as in the original scheme for the first 9 bits. To determine the LSB, the LSB capacitor of the P-side array just needs to be changed, whereas the N-side array remains unchanged. The waveform of the implemented switching scheme is illustrated in Fig. 6.

When using this scheme, the total switching energy is approximately 85.083CV$_{\mathrm{ref}}$$^{2}$ for 10-bit resolution. This is only 6.24\% of the energy consumption of the conventional scheme and half of energy of the V$_{\mathrm{CM}}$-based scheme. Fig. 7 compares the energy consumption of the three switching schemes.

Fig. 4. The proposed 10-bit capacitive DAC with a modified VCM-based switching scheme.
Fig. 5. Example of 3-bit modified VCM-based switching scheme.
Fig. 6. Waveform of the modified VCM-based switching scheme.
Fig. 7. Switching energy versus output code.

3.3 SAR Control Logic

In this SAR ADC, asynchronous control logic is used to avoid using a high-speed clock generator. As illustrated in Fig. 8, the CLKC generator consists of a comparator, 3-input NAND gate, and delay cell. The comparator acts as an inverter with respect to its input clock CLKC, and the NAND gate is an inverter controlled by the EOC signal. Conceptually, this structure makes up a three-stage ring oscillator [6]. After the falling edge of the sampling clock, oscillation starts, and 10 successive CLKC signals are generated. Each bit cycle is triggered at the rising edge of CLKC. Incomplete settling error may heavily degrade the SAR ADC performance, so a variable delay is designed for the first three largest weighted capacitors to allocate longer time for the DAC to fully settle.

As shown in Fig. 9, a SAR shift register implemented by dynamic logic [7] is used to reduce the power consumption. It consists of 10 bit-slice unit, for which the data is clocked by the READY_B signal. In the conversion phase, whenever a comparison is ready, the bit-slice generates a CYCLE signal to control the DAC switch. Simultaneously, the comparator outputs OUTP and OUTN are loaded, latched, and generate the digital output DOUT[9:0]. Fig. 9(c) shows the DAC control logic for both capacitor arrays.

Fig. 8. Asynchronous clock generator.
Fig. 9. SAR control logic (a) Shift register, (b) Circuit schematic of a bit-slice, (c) DAC control logic.

3.4 Comparator

Fig. 10 shows a diagram of the two-stage dynamic comparator [8]. During the reset phase (CLK=0), transistors M$_{5}$ and M$_{\mathrm{6­}}$ pre-charge nodes Fp and Fn to VDD and cause M$_{12}$ and M$_{14}$ to discharge output nodes Vop and Von to ground. In the regeneration phase (CLK=1), M$_{5}$ and M$_{6}$ turn off, which causes nodes Fp and Fn to discharge from VDD with different rates and yields a voltage difference. The two cross-coupled inverters begin to regenerate when the voltage at nodes Fp and Fn are not high enough for M$_{12}$ and M$_{14}$ to keep discharging outputs to ground. The cascode transistors M$_{3}$ and M$_{4}$ are added to help mitigate the kickback noise that occurs while nodes Fp and Fn discharge.

For every bit comparison to be correct, calibration of the comparator’s offset is inevitable for a SAR ADC. One common way to cancel out the offset in the dynamic comparator is to add one more differential pair parallel to the main input pair. The offset can be eliminated by applying an appropriate DC value to this pair. There are various ways to generate this DC voltage. For low power design, a capacitive DAC that does not consume static power is exploited for offset calibration.

The offset calibration scheme uses a binary weight capacitor array. Fig. 11 shows a diagram of the offset calibration part. As a compromise between area and accuracy, a 5-bit DAC is used for this approach (CAL-DAC). Two bit-slices are added to start the calibration. After all 10 bits are determined, CAL_EN goes high, and the calibration process is begun by shorting the two inputs of the comparator (DACp and DACn) to V$_{\mathrm{CM}}$ to determine the polarity of the offset voltage. If the offset is positive, the capacitor array is connected to CAL-N to compensate for the N-side while CAL-P is shorted to GND, and if the offset is negative, the array is connected to CAL-P.

The circuit was implemented using a 2-to-1 multiplexer. To control the calibration process, simple digital logic was implemented. After the CAL_START signal goes high, a 5-bit counter starts running to generate digital calibration bits CAL[4:0]. The asynchronous clock generator is also used for the calibration. The value of V_CAL on the top plate of the DAC gradually increases until the output of the comparator flips, which means that the offset is calibrated.

At this time, EOC goes high and stops the counter. Immediately, the calibration bit CAL[4:0] is then stored in a register to prepare for the next conversion. In the sampling phase, the top plate of CAL-DAC is shorted to ground for resetting. During normal conversion, the calibration digital code that was previously stored in the register is loaded and applied to CAL-DAC.

Fig. 10. Circuit schematic of two-stage dynamic com-parator.
Fig. 11. Comparator offset calibration (a) Binary-weight capacitor array, (b) Calibration logic, (c) Calibration timing.

4. Simulation Results

The 10-bit SAR ADC was implemented using 180-nm CMOS technology and occupies an active area of 385 x 385 ${\mathrm{\mu}}$m$^{2}$. Fig. 12 shows the layout capture of the designed SAR ADC. The comparator and two bootstrapped switches are placed on the left, while the SAR logic and calibration logic are located on the right and below the capacitive DACs.

Metal-insulator-metal (MIM) capacitors were used for the DAC. Each unit capacitor value is 21.2 fF with an area of 4x4 um$^{2}$. This value is chosen to satisfy the matching consideration and the kT/C noise requirement. DC analysis was performed using a slow ramp signal with a resolution of 100 samples/code, as shown in Fig. 13. The SAR ADC achieves a peak differential non-linearity (DNL) and integral non-linearity (INL) of +0.38/-0.37 LSB and +0.41/-0.35 LSB, respectively.

The dynamic performance of the SAR ADC is shown in Fig. 14. The 1024-point fast Fourier transform (FFT) spectrum at 1.22 kHz sinusoid signal indicates a signal-to-noise-and-distortion ratio (SNDR) of 60.29, which results in an effective number of bits (ENOB) of 9.72. The spurious-free dynamic range (SFDR) result is of 72.93 dB.

The power breakdown chart is shown in Fig. 15. The analog parts, digital circuits, and capacitive DACs account for the total power consumptions, which is 4.5 ${\mathrm{\mu}}$W with a 1-V supply. The figure-of-merit (FoM) of the ADC is obtained using the following equation:

$ FOM=\frac{\textit{Power}}{f_{s}.2^{ENOB}} $

The FoM of the proposed SAR ADC is 19.92 fJ/conversion-step. Table 1 presents a summary of the performance in comparison with that of other 10-bit SAR ADCs. The proposed ADC shows good FoM performance with a small area.

Fig. 12. Layout of the SAR ADC (without pad).
Fig. 13. Static performance of the SAR ADC.
Fig. 14. Dynamic performance at 250 kS/s with 1.22-kHz sine wave input (1024-point FFT).
Fig. 15. Power breakdown of each block.
Table 1. Performance summary and comparison.




This work

Process (nm)




Resolution (bits)




Power supply (V)




Sampling rate (kS/s)








ENOB (bits)












Power (µW)




FoM (fJ/conv-step)




Layout area (µm${^2}$)



385 x 385

5. Conclusion

In this paper, a low-power 10-bit SAR ADC was proposed for neural recording applications. A modified V$_{\mathrm{CM}}$-based switching scheme and asynchronous SAR control logic were applied to help reduce the power consumption. The ADC was implemented using 180-nm CMOS technology and consumes 4.2 ${\mathrm{\mu}}$W with a 1-V power supply. The dynamic performance showed an SNDR of 60.29 dB and SFDR of 72.93 when operating at 250 kS/s, as well as an ENOB of 9.72 bits and FoM of 19.92 fJ/conv-step.


This research was funded by the Basic Science Research Program through the National Research Foundation of Korea (NRF), which is funded by the Ministry of Science and ICT (MSIT; NRF-2018R1C1B6003088), as well as the Institute of Information & Communications Technology Promotion (IITP) grant, which is also funded by the MSIT (No. 2017-0-00659). The chip fabrication and EDA tool were supported by the IC Design Education Center (IDEC).


Lopez C. M., et al. , Jan. 2014, An implantable 455-active-electrode 52-channel CMOS neural probe, IEEE J. Solid-State Circuits, Vol. 49, No. 1, pp. 248-261DOI
Salam M. T., Perez Velazquez J. L., Genov R., Jun. 2016, Seizure Suppression Efficacy of Closed-Loop Versus Open-Loop Deep Brain Stimulation in a Rodent Model of Epilepsy, IEEE Trans. Neural Syst. Rehabil. Eng., Vol. 24, No. 6, pp. 710-719DOI
Ramkaj A. T., Strackx M., Steyaert M. S. J., Tavernier F., 2018, A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS, IEEE J. Solid-State Circuits, Vol. 53, No. 7, pp. 1889-1901DOI
Rahimi E., Yavari M., 2014, Energy-efficient high-accuracy switching method for SAR ADCs, Electron. Lett., Vol. 50, No. 7, pp. 499-501DOI
Zhu Y., et al. , 2010, A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS, IEEE J. Solid-State Circuits, Vol. 45, No. 6, pp. 1111-1121DOI
Wu J., Li F., Zhang C., Jan. 2014, An asynchronous SAR ADC with gate-controlled ring oscillator for multi-phase clock generator, in Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014DOI
Liang Y., Zhu Z., Ding R., Oct. 2015, A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS, Microelectronics J., Vol. 46, No. 10, pp. 988-995DOI
Van Der Goes F., et al. , Dec. 2014, A 1.5 mW 68 dB SNDR 80 Ms/s 2${\times}$ interleaved pipelined SAR ADC in 28 nm CMOS, IEEE J. Solid-State Circuits, Vol. 49, No. 12, pp. 2835-2845DOI


Trong Nhan Nguyen

Trong Nhan Nguyen received his B.S. degree in electronics and communi-cations engineering from HCMC University of Technology, Vietnam, in 2018. He received his M.S. degree in electrical and information engineering at Seoul National University of Science and Technology, Seoul, in 2020. His research interests include the design of low-power data converters for biomedical applications.

Hyouk-Kyu Cha

Hyouk-Kyu Cha received B.S. and Ph.D. degrees in electrical engineering at Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2003 and 2009, respectively. From 2009 to 2012, he was a Scientist with the Institute of Microelectronics (IME), Agency for Science, Tech-nology, and Research (A*STAR), Singapore, where he was involved in research and development for analog/RF ICs for biomedical applications. Since 2012, he has been with the Department of Electrical and Information Engineering, Seoul National University of Science and Technology, Seoul, Korea, where he is now an Associate Professor. His research interests include low-power CMOS analog/RF IC and system design for implantable and wearable biomedical devices.