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1. (Department of Electrical and Information Engineering, Seoul National University of Science and Technology / Seoul, Korea {18512108, hkcha}@seoultech.ac.kr )

SAR ADC, Neural recording system, Asynchronous logic, Biomedical device, Low-power

## 1. Introduction

In recent years, closed-loop neural system-on-chips (SoCs) with neural recording and stimulation functions have been widely researched for implantable biomedical devices [1]. These systems can improve patients’ quality of life and are capable of diagnosing and treating various neurological conditions, such as Alzheimer’s disease, epilepsy, and Parkinson’s disease. The neural recording path in neural SoCs is a data acquisition and processing system that observes and understands the electrical activity of the neural networks in the brain.

Fig. 1 shows a block diagram of a typical closed-loop neurostimulation system for seizure treatment [2]. The analog-to-digital converter (ADC) in the neural recording path is an important block that acts as an interface between the analog front-end (AFE) and the digital signal-processing control unit. In such systems, low power consumption is very critical as power resources may be limited in an implant environment, and high power consumption may lead to excessive heating in the surroundings, causing tissue damage.

Neural signals include action potentials (APs or spikes) and local field potentials (LFPs), which generally have a bandwidth ranging from 1 Hz to a few kHz. The amplitude ranges from a few hundred ${\mu}$V to several mV. Therefore, the sampling rate of the ADC does not need to be very high to achieve suitable performance. The successive approximation register (SAR) ADC architecture is the best candidate in this context due to its low power and simple architecture, so it was chosen for this work. A 10-bit SAR ADC with a sampling rate of 250 kS/s was chosen after carefully considering the tradeoff between the power consumption and ADC performance.

The rest of the paper is organized as follows. Section 2 presents the architecture of the proposed SAR ADC. Section 3 discusses the design details of the key function blocks in the ADC. Section 4 presents the key simulation results, followed by the conclusions in Section 5.

## 2. Proposed SAR ADC Architecture

Fig. 2 shows the architecture and timing diagram of the proposed 10-bit SAR ADC for a neural recording system. To achieve good common-mode noise rejection, a fully differential structure is used. A bootstrapped sampling circuit is used to improve the linearity when the input signal ranges from 0 to 1 V. In addition, a modified V$_{\mathrm{CM}}$-based switching scheme is used for a binary weighted capacitive digital-to-analog converter (DAC) to reduce the switching energy.

The differential input signal is sampled on the top plates of the capacitor array, so the MSB is determined directly without any switching activity. A dynamic comparator compares the voltage on the top plate of the capacitor array. Asynchronous SAR control logic stores the comparison results as digital output code and generates control signals for the capacitor switching array. All 10 bits are determined successively until the end of conversion (EOC). When the conversion is done, a time interval is allocated for the comparator offset calibration process before a new conversion occurs.

## 3. Key Functional Blocks

### 3.1 Bootstrapped Switch

In general, the performance of a sample and hold circuit directly and greatly impacts the whole ADC. As the voltage scales down, the sampling circuit becomes a critical part in the SAR ADC because of unwanted effects such as charge injection and clock feedthrough. The bootstrap technique mitigates the problem of signal-dependent on-resistance (R$_{\mathrm{on}}$) of the sampling switch. The on-resistance needs to be kept constant during the sampling phase. When the sampling transistor operates in the deep-triode region, the value of the on-resistance can be expressed as:

## Author

##### Trong Nhan Nguyen

Trong Nhan Nguyen received his B.S. degree in electronics and communi-cations engineering from HCMC University of Technology, Vietnam, in 2018. He received his M.S. degree in electrical and information engineering at Seoul National University of Science and Technology, Seoul, in 2020. His research interests include the design of low-power data converters for biomedical applications.

##### Hyouk-Kyu Cha

Hyouk-Kyu Cha received B.S. and Ph.D. degrees in electrical engineering at Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2003 and 2009, respectively. From 2009 to 2012, he was a Scientist with the Institute of Microelectronics (IME), Agency for Science, Tech-nology, and Research (A*STAR), Singapore, where he was involved in research and development for analog/RF ICs for biomedical applications. Since 2012, he has been with the Department of Electrical and Information Engineering, Seoul National University of Science and Technology, Seoul, Korea, where he is now an Associate Professor. His research interests include low-power CMOS analog/RF IC and system design for implantable and wearable biomedical devices.