GohJu Han1
IshakMohamad Khairi2
-
(School of Electrical and Electronic Engineering, Universiti Sains Malaysia, 14300,
Penang, Malaysia ju.han.goh@intel.com)
-
(School of Electrical and Electronic Engineering, Universiti Sains Malaysia, 14300,
Penang, Malaysia khairiishak@usm.my )
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Keywords
IEEE1588-2008, PTP, Time-triggered, MATLAB, FPGA, Spartan 3E
1. Introduction
The time-triggered embedded system has been proliferating in system-wide synchronization
[1]. Time synchronization has become an important topic in network-embedded systems.
Furthermore, the integrated real-time device design has two architecture methods:
event-triggered (ET) and time-triggered (TT) systems. The Event-triggered system is
unpredictable and responds to the incidence of asynchronous system events. Moreover,
an external interrupt is the prime criterion needed to fulfill the ET system.
On the other hand, the TT system is asymmetrical to the ET system. The TT system
is predictable and will only react at a specific occurrence or event determined before
the system. Furthermore, the TT system only has one interrupt used to drive the scheduler
and is a controlled sequence to obtain only a single event handle at one time
[2].
In a real-time application, the communication time, processing time, and deterministic
play a vital role in a time-triggered system to ensure that the application reacts
precisely to the system and functions correctly. Furthermore, to achieve synchronization
precision and accuracy, this paper proposes the IEEE 1588 protocol to enhance the
communication between the hardware and Ethernet standards. Moreover, the IEEE 1588-2008
protocol has hardware timestamping features implemented. Hardware timestamping is
a clock that timestamps a packet when it arrives, and there is no software delay in
the timestamp. In the IEEE 1588-2008 protocol, the hardware timestamping feature became
the key to the protocol and was implemented into transparent clocks and boundary clocks
by exchanging messages between the master clock and slave clock to achieve higher
accuracy in synchronization
[3]. Furthermore, the IEEE 1588-2008 protocol, which is regarded as the Precision Time
Protocol (PTP), is the Network Time Protocol (NTP)-based improvement protocol to address
the NTP shortcomings and provide a reasonable level of network transmission timing
and synchronization
[4]. Moreover, PTP is used widely in measurement and control systems in industrial automation,
communication, and other technology areas
[5]. Furthermore, the IEEE 1588-2008 protocol positively guarantees timing accuracy within
the sub-microsecond range between the master and slave clocks.
This paper introduces the IEEE 1588-2008 protocol with a TT system on practical
implementation on FPGA hardware. Once the practical hardware has been established,
the performance of the IEEE 1588-2008 protocol on the FPGA is evaluated. Moreover,
this study also utilizes the Ethernet Media data exchange to achieves the precise
time synchronization of PTP
[5]. The offset value of the time stamping of the master clocks can be determined based
on the timestamping of the PTP packet packets Sync Message, Follow up Message, Delay-Rep
and Delay-Resp, and Synchronization.
In addition, the proposed Ethernet communication IEEE 1588-2008 protocol on the
FPGA board enhances the precision synchronization compared to the other Ethernet standards
in the Time-triggered system. Moreover, the approach of the IEEE 1588-2008 protocol
on Time-triggered embedded Ethernet has the advantage of using the Ethernet as standard,
and there is no need for extra synclines. Furthermore, it can have a robust setup
against topology changes, master failure and automatic master selection. Moreover,
this work also increases the accuracy or reduces the delay instead of standard software
synchronization. The proposed system can be applied to real-life applications using
the IEEE 1588-2008 protocol for synchronizing communication models, such as the communication
in robotics between the sensors and actuators [6, 7]. In addition, this system can
also be used to communicate with different nodes for effective communication and precise
synchronization. The related studies of the IEEE 1588-2008 protocol with FPGA are
discussed in the following section.
2. Related Studies
According to [8], the implementation of IEEE 1588 to FPGA shows improved synchronization accuracy
by eliminating the delay jitter method. FPGA is included in the hardware architecture
to catch the timestamps and detect PTP communications, and the ARM processor is used
as the processing core. The project is also executed on a Linux operating system to
handle the synchronization and offset value estimation operation. Clock synchronization
of the master and slave using IEEE 1588 with a clock correction was proposed in [9]. The clock correction features included a self-correction and collaborative correction.
This approach shows that the clock model-based collaborative correction can maintain
the PTP accuracy within 10 ${\times}$10$^{-6}$ seconds in a 10 min prolonged period
after the Master failure on the synchronization.
In reference
[10], the project was implemented on cyclone II FPGA with IEEE 1588. Furthermore, the
stamping PTP message was implemented on PHY to achieve high precision time synchronization
of IEEE 1588. Moreover, the MAC and PHY layer communication used Media Independent
Interface (MII) with hardware ``DM9000 + LXT971A''. In addition, a state machine method
one-hot code was used for the MII module between the MAC and PHY layers. The state
machine included IDLE, PREAMBLE, SFD, UDP, PTP, and SEQUENCEID.
According to
[4], a new architecture for IEEE 1588 synchronization on FPGA is suggested to minimize
the expensive components such as a high-end microcontroller or dedicated IEEE 1588
network hardware. In comparison, FPGA and short broadcast frames are introduced to
a massively distributed device to decrease the CPU power and transmit bandwidth efficiently.
In addition, to synchronize the network, the LVDS transmission line is proposed in
a short frame solution.
The FPGA-based implementation of PTP will eradicate the jitter problems and Ethernet
latency through hardware timestamping, based on reference
[6]. In addition, 10-100 ns precision is achievable using an FPGA-based platform. In
comparison, Altera-based FPGA is the proposed FPGA-based platform. In VHDL, a hardware
timestamp is introduced, and a soft NIOS processor is required to write the stack
of PTP protocols. In addition, utilizing VHDL or Verilog, the FPGA-based platform
shows that the accuracy between Mater and Slave PTP is accomplished with high precision.
Owing to zero jitter and the high accuracy of having a Timestamp meaning, the PTP
protocol's Follow Up Message does not need to be enforced in this document.
Furthermore, research from
[7] used SynUTC technology and IEEE 1588 to introduce the synchronization of high-precision
clocks over Ethernet networks. A high-precision distribution of GPS time and time
synchronization of network nodes connected via standard Ethernet LANs was provided
by SynUTC (Synchronized Universal Time Coordinated) technology. In addition, to manage
the packet latency uncertainties for high precision clock synchronization, an Ethernet
switch is required. Reference
[8], proposed the enabling distribution of the IEEE 1588 protocol using an Ethernet switch
to bridge multiple networking segments between all nodes. Moreover, the switch served
as a master to connect all the nodes by implementing the boundary and transparent
clock theory.
In reference
[9], the project implemented IEEE1588v2 protocol clock synchronization using FPGA and
ARM to improve synchronization accuracy. The method proposed generating hardware timestamping
in the MAC layer to enhance the synchronization system's accessibility and diversity.
On the other hand, the research can be optimized further with software implementation
to simulate the MAC layer's timestamping and compare the data collection between hardware
and software implementation.
According to reference
[10], the research implemented hardware-assist circuitry to enhance the precision synchronization
of the clocks and construct the protocol stack on the control platform of DP83640
in the FPGA-based MAC Layer. Furthermore, the synchronization system uses the data
acquisition card to collect and transfer data from the physical layer to the application
layer. This research paper uses external hardware as an Ethernet receiver to deal
with the timestamping of the PTP messages. Reference
[16] provided details of the IEEE 1588 standard used to synchronize the independent clocks
running on separate nodes of a distributed measurement and control system to achieve
a high degree of accuracy and precision. Furthermore, the research introduces the
IEEE 1588 synchronization process in the FPGA board using the NIOS II system to perform
data collection. On the other hand, the data collection can be optimized using software
data collection compared to an oscilloscope.
Fig. 1. Block Diagram of the Methodology flow.
Fig. 2. Embedded Ethernet Flow Map of Growth.
Previous studies showed the advantages and IEEE 1588 protocol implementation strategies
in different areas. Moreover, the researchers showed the procedure capable of achieving
high Ethernet time synchronization precision. Furthermore, most studies were implemented
with an event-triggered system or a Linux system link. In this project, the IEEE 1588
was implemented using a time-triggered system. In addition, the time-triggered system
could predict and set the requirement to the system without using a Linux system.
The cost of hardware implementation was lower than in previous studies.
3. Methodology
The project covers two parts of the methodology: software and hardware implementation,
as illustrated in Fig. 1. The Xilinx Spartan 3E FPGA Starter Kit Board and Ethernet switch were employed.
Furthermore, the RJ-45 Ethernet adapter and the 83C185 10/100 Ethernet Physical Layer
(PHY) SMSC LAN were used to link the FPGA board and Ethernet switch. Moreover, one
Ethernet switch and two Spartan 3E FPGA boards were used for the proposed assembly.
One of the FPGA boards was configured as the Master Clock, and the Slave Clock was
programmed as the second FPGA board. On the other side, an Ethernet switch served
as the Master Clock and Slave Clock contact bridge.
In addition, the embedded ethernet emulation was simulated utilizing MATLAB Simulink
tools. In MATLAB, the architecture was developed based on the Spartan 3E FPGA hardware
implementation. In comparison, in MATLAB, the developmental characteristics required
two network modules linked to a MAC controller. The network modules were connected
using a virtual network cable.
3.1 Hardware Implementation
$\textbf{(A) Workflow for the Development of an Embedded Ethernet}$
The Spartan 3E FPGA board was chosen in this project due to the development of
a platform that provides the lowest cost logic-optimized, full-featured platform and
consumer-oriented application. Furthermore, the Spartan 3E FPGA used a Media Independent
Interface (MII) as the standard interface to connect the Ethernet, which is suitable
for this project. Fig. 2 shows the development of the embedded Ethernet on the Spartan 3E FPGA board. The
Spartan 3E FPGA Board is compatible using Xilinx ISE 14.7 development tool for programming
and synthesis design.
3.2 Ethernet IP Core
In this study, the Ethernet IP core for IEEE 1588 was sourced from Opencore and
Opensource [17] and implemented into this system. Opencore is licensed under the GNU LGPL license,
and IP is free to access. The IEEE 1588 IP used the current MAC feature of the PTP
SW Protocol stack (PTPD). In addition, the Real-Time Clock (RTC) and Time Stamping
(TSU) of the PTP event packets was also introduced by the IP heart [18].
3.3 Ethernet Controller
An Ethernet controller was set up to transmit and receive the packets. The controller
used the ready RAM block and wrote it to the buffer descriptor for its function. Moreover,
a buffer descriptor was used to monitor the addresses. Furthermore, the setting of
modes and MAC addresses was controlled by the registers. The buffer descriptor can
control the receiving and sending of packets. In addition, to enable them to receive
and transmit, the mode register for transmitter (TX) and receiver (RX) bit needs to
be set in order.
3.3.1 Frame Transmitting Process
Initially, the frame must be placed in the memory for the PTP packets to transmit
the first frame. In comparison, the Ethernet MAC core was connected with 'TX Allow',
with the packets written to the memory. The Tx BD bit was set to 1 for the TX enabling
environment. Once the Ethernet MAC is allowed, the first buffer descriptor will be
read. The Ethernet MAC will point to the related data and begin writing data to the
internal FIFO (First-In-First-Out) after the descriptor is marked as ready. The buffer
descriptor address was incremented after transmission, and the next descriptor was
prepared, with the transmission state written to the buffer descriptor. The loop would
also start again and return to the beginning if the next buffer descriptor is labeled
ready.
3.3.2 Frame Receiving Process
The receive buffer descriptor was labeled as empty for the PTP packets to receive
the first frame. First, the "RX Enable" bit was set to 1 to allow functionality to
be received from the Ethernet. The Ethernet MAC continued to accept frames until the
label was zero. The obtained state was inserted into the buffer descriptor after the
frame had been received and placed into memory. Fig. 3 shows the physical setup of the embedded ethernet system.
$\textbf{(B) Work Plan for the Time Synchronization using IEEE 1588-2008 on Spartan
3E FPGA}$
After the embedded Ethernet design is established, the communication and synchronization
process begins, as shown in Fig. 4. At the initiative of the project, both Spartan 3E FPGA boards are programmed with
the Master clock and Slave clock setup. Both FPGA boards are assigned a dedicated
IP address. The process is started when the Master clock is trying to sync with the
Slave FPGA board. When the message sent from the Master clock to the Slave clock is
not synchronized, the system will perform the synchronization on the Slave clock.
Fig. 3. Hardware practical setup for embedded Ethernet system.
Fig. 4. Flow chart for hardware synchronization using IEEE 1588-2008 Time synchronization.
Synchronization occurs by sending a sync message from the Master clock to the
Slave clock. Moreover, the Master Clock sends a follow-up message to the Slave Clock.
When the Slave Clock received the follow-up Message from the Master Clock, the machine
uses Eq. (1) to measure and obtain ``Master to Slave Delay''.
Next, the ``Master to Slave Delay'' value is registered, and a Delay Request
(Delay$\_$Req) message is sent to the master clock by the slave clock. Once the master
clock has sent the Delay$\_$Req message, the Delay Response (Delay$\_$Resp) message
will be transmitted to the slave clock. The ``Slave to Master Delay'' will be measured
by the machine using Eq. (2).
The machine will measure the offset value for offset$\_$1 and offset$\_$2 using
the ``Master to Slave Delay'' and ``Slave to Master Delay''. Furthermore, a comparison
of the offset value is made to ensure that offset$\_$1 and offset$\_$2 are equal.
Based on the IEEE 1588-2008 theory, the offset value can be calculated using Eqs.
(3) and (4):
The system is synchronized when the value of offset$\_$1 and offset$\_$ 2 are
identical. Therefore, the Slave Clock is synchronized to the Master Clock. On the
other hand, if the offset value is not identical, the system will return to the initial
stage and perform the synchronization again based on the flow chart in Fig. 4 until the Slave Clock is synchronized. Fig. 5 shows the IEEE 1588-2008 synchronization process used to obtain the offset value.
$\textbf{(C) Setup of the FPGA Board}$
Both FPGA boards are programmed with a dedicated IP address and MAC address
shown in the table below. Furthermore, the FPGA Board setup is connected, as shown
in Fig. 3, and the IP address is assigned based on Table 1. Moreover, the Network Switch is preset to the IP address 192.168.1.1, and the subnet
is 255.255.255.0.
Based on the synchronization of the PTP protocol, the Slave FPGA board will
receive the Sync Message and Follow-Up Message from the Master FPGA board. Furthermore,
the Slave FPGA board will send the Delay Req message to the Master FPGA board, and
the Delay Resp message will be submitted to the Slave FPGA board by the Master FPGA
board. Hence, the message is updated for the Slave FPGA board. The time synchronization
result was recorded and shown in Section 4.
Table 1. Assigned IP addresses for the FPGA Board.
|
FPGA Board
|
IP Address
|
MAC Address
|
|
Master
|
192.168.1.44
|
00-18-3E-00-CB-EF
|
|
Slave
|
192.168.1.45
|
00-18-3E-00-AA-2D
|
Table 2. Time synchronization using NTP.
|
Communication of FPGA Board
|
Time synchronization (μs)
|
|
Master to Slave
|
2.34
|
|
Slave to Master
|
2.31
|
Fig. 5. IEEE 1588-2008 Synchronization process.
3.4 Software Implementation
3.4.1 MATLAB Simulation
MATLAB R2015a was used to simulate the hardware implementation of the embedded
Ethernet. The MATLAB-based graphical programming framework gave a robust block library
in Simulink to build its simulation. The simulation is based on the MATLAB library's
Ethernet LAN model to construct the embedded ethernet model for this project. The
embedded ethernet simulation design uses two computers and is shared at 10Mbps, making
it indistinguishable from the hardware implementation. The simulation design requires
three significant blocks to complete the embedded ethernet model design: Application,
MAC controller, and T-Junction. The consumer data model is used in the Application
block. In addition, the MAC controller is used to dictate the shared channel of the
device. The T-junction is used to link the network to the device.
4. Performance Evaluation
4.1 Time synchronization using Network Time Protocol (NTP)
Both Spartan 3E FPGA boards were programmed through ISE 14.7 using the USB A-B
cable, and the time synchronization was captured and recorded in Table 2. Table 2 shows that the transmission from the Master FPGA board to the Slave FPGA board used
was 2.34 μs, and the feedback synchronization time used was 2.31 μs.
4.2 Time Synchronization using PTP (IEEE 1588-2008)
The project applied the IEEE 1588-2008 protocol to the design of time synchronization
after the embedded Ethernet was developed. The program was coded using Verilog programming
languages. Next, the design utilization summary and time synchronization between the
Master and Slave FPGA board of the project were recorded. Table 3 lists the synchronization between the Master and the Slave FPGA board. The time synchronization
tests for four details dependent on the IEEE 1588-2008 protocol: Sync Message, Follow-up
Message, Delay Req Message, and Delay Resp Message. In Table 3, the timeframe required for each knowledge is tabulated.
Table 4 lists the total time used for time synchronization between NTP and PTP. The result
shows that the time used to synchronize the FPGA board was faster than NTP. Moreover,
the PTP proved it was six times faster than NTP.
4.3 MATLAB Simulation with 2 node Ethernet Module
$\textbf{(A) Comparison between a uniform distribution and exponential distribution
on the throughput }$
$\textbf{and channel utilization}$
$\textbf{a. Uniform Distribution}$
Fig. 6 shows the throughput of a uniform distribution in an embedded Ethernet simulation.
The maximum throughput was approximately 700 kbps. Furthermore, the throughput unit
was stationary after 40 seconds as the data transmission was completed. Fig. 7 shows the channel utilization of a uniform distribution in embedded Ethernet. The
result shows that the channel utilization is 13.5 % for a uniform distribution.
Table 3. Time Synchronization using PTP.
|
Communication of FPGA Board
|
Time synchronization (μs)
|
Info
|
|
Master to Slave
|
0.0
|
Sync Message
|
|
Master to Slave
|
0.029
|
Follow up Message
|
|
Slave to Master
|
0.286
|
Delay_Req_Message
|
|
Master to Slave
|
0.515
|
Delay_Resp_Message
|
Table 4. Total time used for time synchronization between NTP and PTP.
|
Protocol
|
Total time used for Time synchronization between the Master and Slave μs
|
|
NTP
|
4.65
|
|
PTP
|
0.83
|
Fig. 6. Uniform distribution for the throughput (kbps).
Fig. 7. Uniform distribution for Channel Utilization.
Fig. 8. Exponential distribution for throughput (kbps).
Fig. 9. Exponential distribution for Channel Utilization.
Table 5. Time Synchronization between the Uniform and Exponential distribution.
|
Distribution
|
Ethernet Communication
|
Time synchronization (μs)
|
|
Uniform
|
Transmitter (TX)
|
2.834
|
|
Receiver (RX)
|
1.502
|
|
Exponential
|
Transmitter (TX)
|
2.668
|
|
Receiver (RX)
|
1.334
|
$\textbf{b. Exponential Distribution}$
Fig. 8 shows the throughput of the exponential distribution in the embedded Ethernet simulation.
The maximum throughput was approximately 18 kbps. Furthermore, the throughput unit
was stationary after 1.5 seconds as the data completed the transmission. Fig. 9 shows the channel utilization of exponential distribution in embedded Ethernet. The
channel utilization was 1.8 % for the exponential distribution.
Table 5 lists the time synchronization between a uniform distribution and exponential distribution.
The time synchronization for the transmitter and the receiver time for both distributions
were similar because the design was simulated with a two-node Ethernet model. Moreover,
the data was collected using the Simulink tool time scope to capture the time synchronization
on the MAC Controller layer for TX and RX.
Furthermore, the time synchronization for Uniform Distribution took longer than
an Exponential Distribution. The throughput data for a Uniform distribution was 700
kbps compared to an Exponential Distribution; the throughout data was 18 kbps. In
addition, the data could carry 700 kilobytes per second (700kbps), meaning that the
time used to carry the data was longer than that to complete the transmission. Therefore,
the Uniform Distribution used more time synchronization time than the Exponential
Distribution.
After generating and evaluating software and hardware implementation results
for the embedded Ethernet, the software implementation for time synchronization was
faster than hardware implementation (Table 6). Owing to the software implementation, a few factors were unaffected by the physical
variable, such as the LAN cable length, packet transmission speed in the LAN, hardware
CPU core use, and memory.
In a previous study [8], the proposed system used a crossover cable as the communication bridge to connect
the Master and Slave clock to eliminate the delay jitter. Moreover, the proposed system
was designed mainly for 1 node communication between the Master and Slave directly.
In contrast, the method proposed in this research has the network communication of
more than one node, with the proven result in section 4. In addition, the proposed
system in this research used the ethernet switch as the communication bridge between
the Master and Slave clocks.
Table 6. Time Synchronization between Hardware and Software implementation on an Embedded
Ethernet.
|
Implementation of Embedded Ethernet
|
Type of Distribution
|
Time Synchronization (μs)
|
|
Hardware
|
|
4.65
|
|
Software
|
Uniform
|
4.336
|
|
Exponential
|
4.002
|
5. Conclusion
The MATLAB simulation and hardware were completed and implemented on the embedded
Ethernet utilizing a time-triggered base communication device. Next, IEEE 1588-2008
clock synchronization was incorporated and integrated into the embedded Ethernet.
The findings showed that in time synchronization, the IEEE 1588-2008 protocol has
better precision and speed in sending the packets compared to the network time protocol.
The second objective was achieved. The result proved that the time synchronization
was six times faster using PTP than NTP. In addition, the time synchronization used
in PTP was 0.83 μs compared to the 4.65 μs for NTP.
6. Future Research
Based on the outcome and inference, the efficiency of the results can be improved
by including more FPGA boards. The collection of synchronization data can be optimized.
The project should use the new FPGA boards from the Spartan family to impart more
functionality and flexibility to the IEEE 1588-2008 protocol.
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Author
Mohamad Khairi Ishak received the B.Eng. degree in Electrical and Electronics Engineering
from IIUM, Malaysia, MSc. in Embedded Systems, from the University of Essex, United
Kingdom, and Ph.D. from the University of Bristol, United Kingdom. Currently, he is
a Senior Lecturer in Mechatronics Engineering at the School of Electrical and Electronic
Engineering, Universiti Sains Malaysia (USM). His research interests are Embedded
systems, Real-Time Control Communications, and Robotics.
Goh Ju Han received his B.Eng. degree in Electronic Computer Engineering from the
University of Malaysia Sarawak (UNIMAS), Malaysia, in 2017, the MSc. in Embedded System
Engineering from the University Sains Malaysia (USM), Malaysia in 2021. Currently,
he works at Intel Corporation as a Software Application Engineer involved in the design
and implementation test development. His research interests include mobile wireless
communication, network system, and image processing.