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1. (Department of Information and Communication Engineering, Hannam University / Daejeon, Korea ilikeit@hnu.kr )

CMOS, Phase noise, Wide tuning range, Hybrid inductor

## 1. Introduction

The demands for high data rates, global mobility, and wide service coverage are rapidly increasing in advanced communication services such as LTE. Scaling down of the CMOS process continuously increases the operating speed and structural complexity of silicon integrated circuits. With CMOS technology, the research for RF transceiver building blocks with wide frequency operability has been progressing. Among the RF building blocks, design of a multi-band and multi-standard integrated VCO with low phase noise characteristics for a system-on-chip (SOC) has attracted considerable interest these days. The research into the theory and analysis of the low phase noise VCO design has been progressing, by the way, it is still challenging work to design a single multi-standard multi-band CMOS VCO with low phase noise [1,2]. Although a large capacitor bank (Capbank) and varactor diodes can be a simple solution for wide tunability, a large area occupation and the phase noise degradation caused by high VCO gain (K$_{\mathrm{VCO}}$) are inevitable. Inductor switching can be another solution for wide tunability; however, switch parasitic resistance worsens the quality (Q) factor of the resonator, and phase noise degradation occurs. In addition, a wide metal strip line is required for a high Q planar spiral inductor -[3], and two large inductors for inductor switching again cause concern over large-area occupation.

A low phase noise LO chain with a very wide tuning range VCO using both bondwire and a planar spiral inductor in the same area is presented in this research. The seven main LTE bands and GSM quad-bands are covered by the proposed hybrid inductor VCO with simple divide-by-2 prescalers. Simultaneously, the most stringent GSM transmitter (Tx) phase noise specification is also satisfied.

## 2. LO Chain Implementation

The different frequency ranges used for LTE and GSM standards are depicted as Table 1. Multi-mode and multi-standard system requires an LO chain with low phase noise and very wide tuning range characteristics. In this research, a divide-by-2 only prescaler is adopted to minimize side effects of other LO structures, such as DC offset, self-mixing, and frequency pulling/pushing -[4]. Therefore, the fundamental frequency range from 3296 to 5380MHz is required to cover the seven main LTE bands and quad-band GSM standard frequencies.

The architecture of the LO chain for LTE and GSM standards is depicted in Fig. 1. For LTE frequency division duplex (FDD) Tx and receiver (Rx) operations, they are active simultaneously, therefore, the LTE FDD Rx band is excluded in this LO chain structure. The design of the LO chain for both wide tunability and low phase noise is challenging.

In addition, for a SAW-less GSM Tx, the most stringent phase noise specification of -162dBc/Hz at a 20MHz offset from the 915MHz carrier frequency is required.

Thus a full-swing dynamic divider, which is shown in Fig. 2(a), is adopted for GSM Tx mode.

With a digital logic gate type structure, a rail-to-rail high voltage swing signal can be maintained from VCO to mixer. This is an efficient way to minimize noise addition. Fig. 2(b) shows a conventional current mode logic (CML) divider, which shows a relatively low voltage swing, in comparison with the dynamic divider, due to the load resistor and current source. For LTE TRx and GSM Rx modes, far out phase noise constraints are not very stringent; therefore, the CML divider is adopted.

##### Table 1. Summary of LTE and GSM frequency bands.
 Standard Band Frequency (MHz) Fundamental carrier (MHz) Division ratio LTE Tx 1 1920 - 1980 3840 - 3960 /2 3 1710 - 1785 3420 - 3570 /2 4 1710 - 1755 3420 - 3510 /2 5 824 - 849 3296 - 3396 /4 7 2500 - 2570 5000 - 5140 /2 38 2570 - 2620 5140 - 5240 /2 40 2300 - 2400 4600 - 4800 /2 GSM Tx 850 824 - 849 3296 - 3396 /4 900 880 - 915 3520 - 3660 /4 1800 1710 - 1785 3420 - 3570 /2 1900 1850 - 1910 3700 - 3820 /2 LTE Rx 1 2110 - 2170 4220 - 4340 /2 3 1805 - 1880 3610 - 3760 /2 4 2110 - 2155 4220 - 4310 /2 5 869 - 894 3476 - 3576 /4 7 2620 - 2690 5240 - 5380 /2 38 2570 - 2620 5140 - 5240 /2 40 2300 - 2400 4600 - 4800 /2 GSM Rx 850 869 - 894 3476 - 3576 /4 900 925 - 960 3700 - 3840 /4 1800 1805 - 1880 3610 - 3760 /2 1900 1930 - 1990 3860 - 3980 /2

## 3. VCO Design

To design a low phase noise VCO with a wide tuning range and low power dissipation, an NMOS-only structure is selected. This topology has just two MOSFETs for an active gm-switching core, which is helpful for maximizing frequency tuning range due to lower parasitics. For the phase noise, the NMOS-only type enables a higher output voltage swing than the complementary type as the bias current increases -[4]. For phase noise in the oscillator, Leeson’s proportionality is a well-known model -[5]:

##### (1)
$L\left\{\Delta \omega \right\}\propto \frac{1}{V_{o}^{2}}\cdot \frac{kT}{C}\cdot \left(\frac{\omega _{o}}{Q}\right)^{2}\cdot \frac{1}{\omega _{m}^{2}}$

In Eq. (1), the phase noise is dependent on signal amplitude Vo, where kT/C noise is shaped with the LC tank in the frequency domain and is normalized to the signal power in the tank. Therefore, the NMOS-only VCO core type can present better phase noise than the complementary type as the bias current increases.

After selecting the optimum FET size for the gm-cell, considering power consumption and phase noise, the characteristics of a switched Capbank and an inductor decide the multi-band and multi-standard VCO performance. On the whole, the Q factor of an inductor is worse than that of a Capbank. Therefore, for signal purity in the transceiver, high Q factor inductor design is a cardinal feature. A custom designed planar spiral inductor shows a good Q factor value of about 20. However, a relatively large inductor size of about 500${\mathrm{\mu}}$m is required. For the Q factor of a bondwire inductor, values above 25 can be obtained in the frequency band of interest -[6]. Since the inductance grows linearly with increasing lengths of the bondwire, it can be modified by changing the bondwire height and the distance between the bond pads. In general, the bondwire has a three-dimensional structure, and other circuit blocks can be placed under the bondwire.

Fig. 3 depicts the proposed VCO structure. A planar spiral inductor is placed under the bondwire, which is the hybrid inductor structure. The bondwire and spiral inductor share a center-tapped bias line that is connected to a regulator. Using an EM simulator, the conventional planar inductor is designed for low band (LB) VCO, and the bondwire inductor is designed for high band (HB). The bondwire inductor has an inductance of 0.8nH and a peak Q of about 30 at 4GHz, while the spiral inductor has a 1.6nH inductance and a peak Q of about 19 at 3GHz. Fig. 4 shows the hybrid inductor simulation results.

For LO frequency planning in this paper, a VCO tuning range of about 50% is required for LTE and GSM standards. It is difficult to satisfy both phase noise and wide tunability requirements with same LC tank for the very wide frequency tuning range standards. Therefore, the Capbank is separately designed for HB and LB with bondwire and planar spiral inductor, respectively. For switching the LC tank between HB and LB, inductor switching is also required. However, the switch (S/W) loss in the conventional switched inductor structure degrades the Q factor of the resonator and the phase noise. Although a large MOS S/W in the inductor structure can have less loss, the frequency tuning range can be degraded by larger parasitic capacitance. The proposed hybrid inductor VCO is switched to HB or LB by activating each gm-cell core without any MOS S/W in the inductor itself, and it does not experience Q degradation caused by parasitic components of the S/W. Thus, the trade-off between tuning range and phase noise can be relieved, in comparison with the inductor switching method -[7].

For varactors and a switched Capbank, proper design is required to attain a reasonable K$_{\mathrm{VCO}}$ for stable PLL operation and to avoid phase noise degradation. For coarse tuning of the proposed VCO, a binary-weighted eight-bit switched capbank with a sufficient frequency margin to overcome the frequency shift due to PVT fluctuations is used. And for fine tuning, accumulation-type MOS varactors are used.

As for the size issue, the inductor commonly occupies almost the entire silicon area in the layout of an LC VCO. By placing two inductors in the same location, the proposed structure can save a lot of silicon area. And to minimize power consumption, the VCO bias current can be varied using three-bit binary weighted bias resistor control for each frequency band. A trade-off between phase noise and power consumption is acquired with this programmability, which is necessary for multi-standard and multi-band VCOs.

## 4. Experimental Results

Considering the multi-band, multi-standard, and low phase noise design issues, a fully integrated LO chain is designed and implemented in 65nm CMOS technology. Fig. 5(a) is a microphotograph of the proposed LO chain with a hybrid inductor VCO. The chip size is 1 mm$^{2}$. As depicted in Fig. 5(b), the measurement results show that the proposed VCO carrier signal is tunable from 2460 to 3820MHz for the LB with a spiral inductor, and is tunable from 3350 to 5430MHz for the HB with the bondwire inductor. A three-dimensional structure of the bondwire inductor minimizes electromagnetic coupling with a planar spiral inductor, and a shared bias line is connected to each inductor center tap. Band switching is achieved by activating each gm-cell core without the use of a switching device in the inductor itself. At any given moment, only one gm core is enabled. Therefore, for the HB frequency tuning range and phase noise characteristics, there is almost no degradation caused by a turned-off LB block. However, a parasitic capacitance of about 150 fF is analyzed from the measured HB frequency tuning range, which is generated from the bonding pads and thick metal signal lines around the capbank and gm cell.

The resulting full frequency tuning range is from 2460 to 5430MHz, which is up to 75% of the mid-frequency for total dual band operation. The LTE 700 band -[8] is also included in frequency planning for the LB VCO. Fig. 6(a) depicts the measured phase noise results after 1/2 divider, which are -128dBc/Hz at 1MHz offset from 1492MHz LB VCO carrier frequency and -121dBc/Hz at 1MHz offset from 2299MHz HB VCO carrier frequency, which satisfy the LTE phase noise specifications. The VCO core operates at 1.2V, and consumes 8.5mA. As depicted in Fig. 6(b), the phase noise at 20MHz offset from 915MHz carrier after 1/4 divider is -164.1dBc/Hz with 18mA VCO core current, which exceeds the most stringent GSM Tx phase noise specifications. Fig. 6(c) depicts the improvement results of phase noise at 20MHz offset as LB VCO bias current increases.

Widely used figures of merit for VCO are FOM and FOMT -[9]. FOMT can consider the degradation caused by tuning range. FOM and FOMT are defined as follows:

##### (2)
$FOM=L\left(f_{off}\right)-20\log \,\left(\frac{f_{o}}{f_{off}}\right)+10\log \,\left(\frac{P_{DC}}{1mW}\right)$
##### (3)
$FOMT=FOM\hbox{--}20\log _{10}\left(TR\% /10\right)$

where L(f$_{\mathrm{off}}$) is the phase noise at offset frequency f$_{\mathrm{off}}$, P$_{\mathrm{DC}}$ is VCO power consumption in milliwatts, f$_{\mathrm{o}}$ is the oscillation frequency, and TR% is the tuning range percentage. The measured FOM at 1MHz offset for 1492MHz LB VCO and 2299MHz HB VCO carrier frequency after 1/2 divider are -181.4 and $\hbox{-}$178.1dBc/Hz, respectively. The measured FOMT are -194.1 and -184.7dBc/Hz for LB and HB VCOs, respectively. The measurement results are summarized in Table 2 and compared with other low phase noise VCOs. Considering the wide tuning range of 75%, the measured FOM and FOMT are quite comparable to previously published results.

##### Table 2. VCO performance summary and comparison.
 VCO Tech Freq. Range (MHz) Power (mW) P/N @ 1MHz (dBc/Hz) FOM (dBc/Hz) FOMT (dBc/Hz) [10] 0.35µm Bi-CMOS 5130-5680 13.5 -117 -180.7 -180.9 [11] 180nm CMOS 2220-2940 3.6 -122.5 -186.1 -195.0 [12] 28nm CMOS 4700-5400 0.5 -116 -193.7 -196.5 [13] 65nm CMOS 1820-2530 0.55 -113 -183.7 -193.9 This Work LB 65nm CMOS 2460-3820 10.2 -128 -181.4 -194.1 HB 3350-5430 -121 -178.1 -184.7

## 5. Conclusion

A low phase noise, multi-band, multi-standard LO chain for LTE and GSM standards is proposed. The seven main LTE bands and quad-band GSM standard frequency ranges are covered by wide frequency tunability of the LO chain with a hybrid inductor VCO. The hybrid inductor structure is composed of both bondwire and spiral inductor and saves large silicon area. The measured results show a 75% tuning range from 2460 to 5430MHz, and phase noise of -128 and -121dBc/Hz at 1MHz offset from 1.5GHz LB and 2.3GHz HB carrier frequency, respectively, after 1/2 divider. The VCO core consumes 8.5mA from a 1.2V supply. And the phase noise at 20MHz offset from 915MHz carrier after 1/4 divider is -164.1dBc/Hz with a 18mA VCO core current. This performance proves that the proposed LO chain can be used for LTE bands and SAW-less GSM transceiver, and confirms that a good trade-off among wide tunability, silicon area efficiency, and phase noise is achieved from the proposed LO chain with a hybrid inductor VCO.

### ACKNOWLEDGMENTS

This research was supported by the National Research Foundation of Korea under Grant NRF-2017R1D1A1B03036412; IDEC(EDA Tool, MPW).

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## Author

##### Seonghan Ryu

Seonghan Ryu received the B.S. degree in electronics engineering from Kyungpook National University, Daegu, Korea, in 1998, and the M.S. and Ph.D. degree in electronic and electrical engineering from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2000 and 2005, respectively. In 2002, he was a visiting researcher of electrical engineering Dept. with the California Institute of Technology (CALTECH), Pasadena, U.S. And from 2005 to 2007, he was with Samsung Electronics, Yongin, Korea. From 2007 to 2008, he was with Defense Agency for Technology and Quality (DTaQ), Seoul, Korea. Since 2008, he has been with the Department of Information and Communication Engineering, Hannam University, Daejeon, Korea, where he is now a professor. From 2013 to 2014, he was a visiting scholar of electrical and computer engineering Dept. with the Georgia Institute of Technology (GeorgiaTech), Atlanta, U.S. His research interests include multi-mode/multi-standard RF CMOS transceiver design for wireless communication, RF system architectures, millimeter-wave circuits and Bio-inspired microsystems with CMOS technologies