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REFERENCES

1 
Jain S., Lin L., Alioto M., 2017, Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy Point, IEEE Trans. Circuits. Syst. I, Vol. 64, No. 12, pp. 3115-3125DOI
2 
Wang Q., Li P., Kim Y., 2015, A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 23, No. 8, pp. 1471-1474DOI
3 
Yang Y., Kim Y., 2020, Approximate Digital Leaky Integrate-and-fire Neurons for Energy Efficient Spiking Neural Networks, IEIE Trans. Smart Process. Comput., Vol. 9, No. 3, pp. 252-259DOI
4 
Kim Y., Zhang Y., Li P., 2015, A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing, J. Emerg. Technol. Comput. Syst., Vol. 11, No. 4, pp. 38:1-38:25DOI
5 
Wang Q., Kim Y., Li P., Aug. 2014, Architectural Design Exploration for Neuromorphic Processors with Memristive Synapses, IEEE Int. Conf. Nanotechnology, pp. 962-996DOI
6 
Xu S., Schafer B. C., 2019, Toward Self-Tunable Approximate Computing, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 27, No. 4, pp. 778-789DOI
7 
Raha A., et al. , 2017, Quality Configurable Approximate DRAM, IEEE Trans. Comput., Vol. 66, No. 7, pp. 1172-1187DOI
8 
Zhu N., et al. , 2010, Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and its Application in Digital Signal Processing, IEEE Trans. Very Large Scale. Integr. (VLSI) Syst., Vol. 18, No. 8, pp. 1225-1229DOI
9 
Lee J., et al. , 2020, Approximate Adder Design with Simplified Lower-Part Approximation, IEICE Electron. Express, Vol. 17, No. 15, pp. 1-3DOI
10 
Mahdiani H. R., et al. , 2010, Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications, IEEE Trans. Circuits. Syst. I, Vol. 57, No. 4, pp. 850-862DOI
11 
Dalloo A., et al. , 2018, Systematic design of an approximate adder: the optimized lower part constant-OR adder, IEEE Trans. Very Large Scale. Integr. (VLSI) Syst., Vol. 26, No. 8, pp. 1595-1599DOI
12 
Kim Y., 2019, An Accuracy Enhanced Error Tolerant Adder with Carry Prediction for Approximate Computing, IEIE Trans. Smart Process. Comput., Vol. 8, No. 4, pp. 324-330DOI
13 
Kim Y., 2019, A Novel Approximate Adder with Enhanced Low-cost Carry Prediction for Error Tolerant Computing, IEIE Trans. Smart Process. Comput., Vol. 8, No. 6, pp. 506-510DOI
14 
Seo H., Yang Y. S., Kim Y., 2020, Design and Analysis of Approximate Adder with Hybrid Error Reduction, Electronics, Vol. 9, No. 3, pp. 471:1-471:13DOI
15 
Akbari O., et al. , 2018, RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder, IEEE Trans. Circuits. Syst. II: Exp. Briefs, Vol. 65, No. 8, pp. 1089-1093DOI
16 
Kim Y., Zhang Y., Li P., Nov. 2013, An Energy Efficient Approximate Adder with Carry Skip for Error Resilient Neuromorphic VLSI Systems, in IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 130-137DOI
17 
Kim Y., Zhang Y., Li P., 2015, Energy Efficient Approximate Arithmetic for Error Resilient Neuromorphic Computing, IEEE Trans. Very Large Scale. Integr. (VLSI) Syst., Vol. 23, No. 11, pp. 2733-2737DOI
18 
Lee J., Seo H., Kim Y., Oct. 2020, Design of a Low-Cost Approximate Adder with a Zero Truncation, Int. SoC Design Conf., pp. 69-70DOI
19 
Seo H., Yang Y. S., Kim Y., Oct 2020, An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation, Int. SoC Design Conf., pp. 143-144DOI
20 
Seo H., Kim Y., Nov. 2021, A New Approximate Adder with Duplicate-Constant Scheme for Energy Efficient Applications, IEEE Int. Conf. Consumer Electronics-Asia, pp. 1-2DOI
21 
Gupta V., et al. , 2013, Low-Power Digital Signal Processing Using Approximate Adders, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol. 32, No. 1, pp. 124-137DOI
22 
Raha A., Jayakumar H., Raghunathan V., 2016, Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 24, No. 3, pp. 846-857DOI