1. Introduction

Burn-in testing is a process in which a test system drives a tested device at high temperature and applies a predetermined stress to it to detect an initial failure ^[1]. This process can test the reliability of semiconductor devices. However, various failures and defects may occur in the electrical path as the device operates for a long time at high temperature ^[2]. Stresses and loads can damage the materials of the socket or board or create defects through electrical, physical, or chemical processes.

Several factors are known to induce defects during burn-in tests, such as solder voids, package warpage, electrochemical migration, and intermetallic formation ^[3-13]. Voids occur due to flux gas, soldering contamination, and pores inside a solder ball and substrate ^[3-5]. Voids can cause open defects such as solder joint cracks and board delamination due to long operation at high temperatures. Moreover, large voids in adjacent solder balls can cause short defects.

Package warpage is caused by a mismatch in the coefficients of thermal expansion between the epoxy mold compound and the printed circuit board (PCB) ^[6,7]. Package warpage can lead to open defects in an outer solder ball and short defects in a central solder ball. Electrochemical migration is known to occur due to the migration of ionic species during electrochemical reaction ^[8-10]. The movement of ions is accelerated by the electrical field and can cause an electrical short.

Several metallic elements may inter-diffuse beyond the contact interface to form an alloy mixture ^[11,12]. These intermetallic compounds (IMCs) are very brittle and thus weaken the interface between metals ^[13]. Joule heating caused by high current accelerates IMC formation and eventually causes failure. These factors cause open or short defects in a socket, circuit board, or tested device.

Several methods have been reported to detect defects in devices, sockets, and boards. Table 1 shows a summary of these methods. One type of inspection method detects and classifies defects on a PCB using image processing ^[14-16]. Defects in solder joints of a processor socket have also been detected using X-rays ^[17,18]. To obtain clearer measurements and analyses, test samples were destroyed, and optical micrographs, X-ray images, and scanning electron microscopy (SEM) data were obtained. This destructive defect analysis provides a clear image, but the test sample may be damaged, and additional defects may occur in preparation for measurement.

In general, a daisy-chain structure is used to check the continuity of an electrical path between a package, PCB, and socket ^[19,20]. This daisy chain connects each component and forms a closed loop. It has been used to monitor resistance in reliability tests for semiconductor devices and components ^[21]. S$_{11}$ measurement and analysis were proposed to classify and locate defects in through-silicon-via (TSV) daisy-chain structures ^[22]. If failure occurs in the closed loop, the loop resistances differ from the normal values.

In addition, various failures may occur in a package, PCB, or socket during a burn-in test, resulting in open defects or short defects. These defects have a significant effect on the electrical performance of semiconductor devices and components. Thus, we propose a method for defect-detection analysis of burn-in sockets and boards. The detection and location of the defects in the electrical path are analyzed to connect sockets and boards to form a daisy-chain path and to calculate the S-parameter and Z-parameter.

2. Method of Defect Detection

2.1 Daisy-chain Path using Coplanar Waveguide

We propose a method for the detection of defects in a burn-in socket by applying daisy-chain and coplanar waveguide (CPW) structures. The burn-in socket has multiple contact pins to supply power to the tested device and for test measurements. Therefore, a method is required to inspect multiple pins at the same time to detect defects effectively.

Fig. 1 shows the configuration of the burn-in socket and daisy-chain boards. A CPW pattern is designed on the board, and a burn-in socket is placed between the top and bottom PCBs. The burn-in socket has 30 contact pins with 6 horizontal rows and 5 vertical rows. The boards have dimensions of 4.7 ${\times}$ 5.5 ${\times}$ 0.27 mm$^{3}$ and a socket height of 4.28 mm. The CPW trace on the boards and the contact pins of the socket were connected to create a daisy-chain path, and all contact pins in the socket were placed on this path.

Fig. 2 shows the CPW patterns designed on the daisy-chain boards. The CPW structure can be implemented as a single layer and has an advantage of being able to connect contact pins simultaneously through signal lines and ground lines. To form a daisy-chain path, the CPW traces of the top and bottom PCBs were designed differently. The trace pitch was set to 0.8 mm, which is the same as the pitch of a contact pin in a socket. The CPW trace width was set to 0.5 mm to obtain a characteristic impedance of 50 ${\Omega}$.

Fig. 3 shows a top view and cross-sectional view of the daisy-chain path. The daisy-chain path is formed by the configuration and arrangement of the top PCB, bottom PCB, and socket. Signal S in the figure starts from Port 1 and passes through the top PCB, socket, and bottom PCB several times in the upper or lower directions to form a daisy chain before reaching Port 2. The test signal passes along this path to form an electrical circuit. The electrical paths of the signal and ground are indicated by dotted lines in Fig. 3.

Fig. 1. Configuration of burn-in socket and daisy-chain boards.

Fig. 2. Daisy-chain boards and their coplanar waveguide patterns (a) Top printed circuit board, (b) Bottom printed circuit board.

Fig. 3. Top (a) and cross-sectional, (b) views of boards and socket

Fig. 4. Defect location and type in the boards and socket (a) Defect locations on the board, (b) Open and short defects in the socket and boards.

Fig. 5. Reflection loss of daisy chain path with and without defects.

Fig. 6. Insertion loss of daisy chain path with and without defects.

3. Analysis of Defect Detection

To verify that a defect can be detected using S-parameter analysis, a defective daisy-chain path was compared to a path without any defects. First, the daisy-chain paths with and without defects were modeled. Next, the S-parameters of the two models were calculated, and their results were compared. Fig. 5 shows the reflection loss (S$_{11}$) of the daisy-chain paths.

Reflection increases as the S$_{11}$ curve approaches 0 dB. Open defects and short defects have high losses (between 0 and -2 dB) over all frequency ranges. Both types of defects lead to impedance discontinuities in the daisy-chain path. This causes signal reflections at the defect location, resulting in increased reflection loss. In contrast, a non-defective path shows a completely different S$_{11}$ curve. There is no impedance discontinuity from a defect on the path, so the reflection loss is not high. However, loss occurs due to only the mismatch in the characteristic impedance between the CPW trace and the contact pin.

Fig. 6 shows the insertion loss (S$_{12}$) of the daisy-chain path. The closer the S$_{12}$ graph is to 0 dB, the better the signal is transmitted without loss. A non-defective path shows low loss in all frequency ranges, and signals in this path are transmitted without significant loss. However, open defects and short defects result in a value of less than -40 dB in DC and higher insertion loss compared to non-defective paths. This result demonstrates that signals are hardly transmitted along the electrical path. This verifies that the defects in the daisy-chain path can be detected by comparative analysis of the S-parameters of models with and without defects.

The defect location changes along the daisy-chain path, so the resulting changes in the S-parameter were investigated. Fig. 7 shows the reflection loss (S$_{11}$) from open defects placed along the daisy-chain path. As shown in Fig. 4, Point 1 to Point 6 denote the defect locations along the electrical path. Fig. 7 shows that the S-parameter curves can be divided into 3 categories according to the defect locations. Point 1 and Point 6 are somewhat different in some frequency bands but show similar curves overall. Point 2 and Point 5 show similar curve characteristics, whereas Point 3 and Point 4 show almost the same curve in all frequency bands.

These three different types of curves demonstrate that each type of open defect is located differently on the daisy-chain path. However, Point 3 and Point 4 cannot be distinguished by the characteristics of the S-parameter curves alone. Therefore, the location of the defects cannot be determined, even though the open defects can be detected.

Fig. 8 shows the insertion loss (S$_{12}$) from open defects placed along the daisy-chain path. The curves of the insertion loss can also be classified in the same way as in Fig. 7. Point 1 and Point 6, Point 2 and Point 5, and Point 3 and Point 4 are almost the same in all frequency bands and look like pairs. The locations of the open defects cannot be specified with the same curve characteristics. As shown in Fig. 8, the open defect shows significant insertion loss of less than -20 dB in the low-frequency band below 0.5 GHz. However, the open defect shows a low loss of approximately -5 dB in the high-frequency band above 1.5~GHz. Unlike in the low frequency band, these results show that the high-frequency signals can pass through the narrow gap at the open defect point through electromagnetic coupling.

The S-parameters of the short defects were calculated to analyze the effect of the defect location on the daisy-chain path. Fig. 9 shows the reflection loss (S$_{12}$) of the short defects. Similar to the trend in Fig. 7, the S-parameter curves can be classified into three types. Point 1 and Point 6 are short defects located in each port. They have some differences in certain frequency bands but show similar curves overall.

Point 2 and Point 5 also show similar curve characteristics in all frequency ranges. However, Point 3 and Point 4 show almost the same graph but are located near the center of the electrical path and adjacent to each other. Comparing Figs. 7 and 9, the short defects show significantly different S-parameters and curve tendencies from those of open defects despite having the same locations. However, as with the reflection loss analysis of the open defects, the three types of curves prove that the positions of the short defects are different along the daisy-chain path.

Fig. 10 shows the insertion loss (S$_{12}$) for the short defect placed in the daisy-chain path. The reflection loss is approximately -10 dB or less over all frequency ranges. There is a significant loss when the signals start from Port 2 and reach Port 1 along the electrical path. In other words, signals are not effectively transmitted along the daisy-chain path. These results indicate that significant reflection loss occurs on the path, which proves that defects are present.

As shown in Fig. 8, the insertion loss of an open defect has a large difference in the low and high frequency bands. On the other hand, short defects have the same level of loss at low and high frequencies. As shown in Figs. 8 and 10, the large difference in the trends of these S-parameter curves makes it possible to distinguish between short and open defects.

We propose using Z-parameter analysis as a method to distinguish defect locations in the daisy-chain path. The Z-parameter has the advantage of providing the capacitive and inductive characteristics more intuitively, so it was used to analyze defects. As the frequency increases, the impedance of the capacitive load gradually decreases, while the impedance of the inductive loads increases continuously. Therefore, the impedance $\textit{Z}$ of the electrical path can be expressed as:

where w is the angular frequency, $\textit{R}$ is the resistance, $\textit{L}$ is the inductance, and $\textit{C}$ is the capacitance of the electrical path.

Fig. 11 shows the Z-parameter (Z$_{11}$) for open defects placed at different locations on the daisy-chain path. The open defects have a capacitive characteristic, so their impedances gradually decrease in the frequency range below about 1 GHz. However, in the frequency band above 1 GHz, the inductance is the dominant circuit component, and the impedances increase with frequency. The inset of the figure shows an enlargement of the Z-parameter curves in the region in the circle.

As the open defect moves away from Point 1, the physical distance of the trace from which the signal starts (from Port 1) to reach the defect location increases, and the capacitance of the trace also increases. Therefore, as the point number increases, the impedance of an open defect decreases. The locations of the open defects can be distinguished because these defects have different impedances. In other words, different impedance curves appear at each point of the open defects.

Fig. 12 shows the Z-parameter (Z$_{11}$) for short defects at different locations along the daisy-chain path. The short defects have an inductive characteristic and make the daisy-chain path have an inductance-dominant circuit component. Therefore, the impedance of the defective path increases up to the low and mid-frequency bands.

As shown in Fig. 4, the locations of the short defects are arranged differently. As the point number of the short defect increases, the electrical length of the trace from Port 1 to the short defect increases, and thus, the impedance increases. Different impedance curves appear in each order of the points of short defects, as shown in Fig. 12. The results of Figs. 11 and 12 demonstrate that Z-parameter analysis can distinguish the type and location of defects in a daisy-chain path.

Fig. 7. Reflection loss with location of open defect on daisy-chain path.

Fig. 8. Insertion loss with location of open defect on daisy-chain path.

Fig. 9. Reflection loss with location of short defect on daisy-chain path.

Fig. 10. Insertion loss with location of short defect on daisy-chain path.

Fig. 11. Z-parameter with location of open defect on daisy-chain path.

Fig. 12. Z-parameter with location of short defect on daisy-chain path.

4. Conclusion

A method of defect-detection analysis has been proposed for burn-in sockets and boards. In this method, circuit boards with CPW traces were placed and connected above and below the socket, resulting in a daisy-chain path. Defects were placed at 6 points along the path, and the S-parameter of the path was calculated. The detection of defects on the path was verified by comparing the calculation results of the models with and without defects. Both open and short defects cause impedance discontinuity in the daisy-chain path and change the S-parameter and Z-parameter. Therefore, it was verified that S-parameter analysis can be used to detect defects and their type.

The S-parameter analysis method can detect defects with changes in their location, but some S-parameter curves were very similar to each other, so the defect location could not be identified. For this reason, Z-parameter analysis was used to identify the defect location along a daisy-chain path. Movements of the defect along the path cause changes in the capacitance and inductance, eventually resulting in changes in the Z-parameter. Therefore, it was proven that Z-parameter analysis can be used to distinguish the type and location of a defect.