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REFERENCES

1 
Park M. C., Lee B. W., Kim G. M., Kim D. H., 1993, Compact and Fast Multiplier Using Dual Array Tree Structure, IEEE Int. Symp. on Circuit and Systems, Chigago, Vol. 3, pp. 1817-1820DOI
2 
Wallace C.S., 1964, A Suggestion for a Fast Multiplier, IEEE Trans. Electron. Compt., Vol. 13, No. 1, pp. 14-17DOI
3 
Dadda L., 1965, Some Schemes for Parallel Multipliers, Alta FrequenzaGoogle Search
4 
Mehta P., Gawali D., 2009, Conventional versus Vedicmathematical method for Hardware implementation of a multiplier, IEEE Int. Conf. on Advances in Computing, Control, Telecommun.Technologies, pp. 640-642DOI
5 
Booth A. D., 1951, A Signed Binary Multiplication Technique, Jour. ofMech. Appl. Math., Vol. 4, pp. 236-240DOI
6 
Yeh W. C., Jen C. W., 2000, High-Speed Booth Encoded Parallel Multiplier Design, IEEE Trans. on Compt., Vol. 49, No. 7, pp. 692-701DOI
7 
Schwarz E. M., III R. M. A., Sigal L. J., 1997, A radix-8 CMOS S/390 multiplier, in Proc. 13th IEEE Symp. Comput. Arithmetic (ARITH), pp. 2-9DOI
8 
Colon-Bonet G., Winterrowd P., 2008, Multiplier evolution: A familyof multiplier VLSI implementations, Comput. J., Vol. 51, No. 5, pp. 585-594DOI
9 
Riedlinger et al. R., 2012, A 32 nm, 3.1 billion transistor, 12 wide issue itanium processor for mission-critical servers, IEEE J. Solid-State Circuits, Vol. 47, No. 1, pp. 177-193DOI
10 
Rao M., Dubey S., 2012, A high speed and area efficient Booth recoded Wallace tree multiplier for fast arithmetic circuits, Microelectronics and Electronics (Prime Asia), 2012 Asia Pacific Conference onPostgraduate Research, pp. 220-223DOI
11 
Yoon M., 2019, Design of A Fast Multiplier with (m, 3)-Adders, IJERT, Vol. 12, No. 10, pp. 1757-1763URL
12 
Neil H.E. Weste , David M. Harris , Kamran , 2010, Principles of CMOS VLSI Design: A systems perspective, Pearson, Fourth EditionGoogle Search
13 
Pilato L., Saponara S., Fanucci L., 2016, Performance of digital adder architectures in 180nm CMOS standard-cell technology, 2016 International Conference on Applied Electronics (AE), pp. 211-214DOI
14 
Ghafari S., Mousazadeh M., Khoei A., Dadashi A., 2019, A New High-speed and Low area Efficient Pipelined 128-bit Adder Based on Modified Carry Look-ahead Merging with Han-Carlson Tree Method, 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems", pp. 157-162DOI